HEF40161

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161B

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161B

4-bit synchronous binary counter with asynchronous reset;

DESCRIPTION\nThe HEF40161B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0 to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count enable trickle (CET)), buffered outputs from all four bit positions (O0 to O3) and a terminal count output (TC).\nOperation is fully synchronous (except for the MR input) and occurs on the LOW to HIGH transition of CP. When PE is LOW, the next LOW to HIGH transition of CP loads data into the counter from P0 to P3 regardless of the levels of CEP and CET inputs.\nWhen PE is HIGH, the next LOW to HIGH transition of CP advances the counter to its next state only if both CEP and CET are HIGH; otherwise, no change occurs in the state of the counter. TC is HIGH when the state of the counter is 15 (O1 to O3 = HIGH) and when CET is HIGH. A LOW on MR sets all outputs (O0 to O3 and TC) LOW, independent of the state of all other inputs. Multistage synchronous counting is possible without additional components by using a carry look-ahead counting technique; in this case, TC is used to enable successive cascaded stages. CEP, CET and PE must be stable only during the set-up time before the LOW to HIGH transition of CP.

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HEF40161BD

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161BF

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161BN

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161BP

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161BT

4-bit synchronous binary counter with asynchronous reset

DESCRIPTION TheHEF40161Bisafullysynchronousedge-triggered4-bitbinarycounterwithaclockinput(CP),anoverridingasynchronousmasterreset(MR),fourparalleldatainputs(P0toP3),threesynchronousmodecontrolinputs(parallelenable(PE),countenableparallel(CEP)andcountenab

PHI

HEF40161BD

4-bit synchronous binary counter with asynchronous reset;

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