12-stage binary counter

DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

文件：42.85 Kbytes 页数：5 Pages

PHI

飞利浦

12-stage binary counter

DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

文件：42.85 Kbytes 页数：5 Pages

PHI

飞利浦

12-stage binary counter

DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

文件：42.85 Kbytes 页数：5 Pages

PHI

飞利浦

12-stage binary counter

DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

文件：42.85 Kbytes 页数：5 Pages

PHI

飞利浦