4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

文件：73.23 Kbytes 页数：8 Pages

PHI

PHI

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

文件：73.23 Kbytes 页数：8 Pages

PHI

PHI

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

文件：73.23 Kbytes 页数：8 Pages

PHI

PHI

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

文件：73.23 Kbytes 页数：8 Pages

PHI

PHI

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

文件：73.23 Kbytes 页数：8 Pages

PHI

PHI

4-bit bidirectional universal shift register

DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), an

文件：73.23 Kbytes 页数：8 Pages

PHI

PHI

4-bit bidirectional universal shift register

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