Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

文件：58.08 Kbytes 页数：5 Pages

PHI

飞利浦

Tolerant of slow clock rise and fall times

文件：108.33 Kbytes 页数：15 Pages

恩XP

Dual 4-bit static shift register

General description\nThe HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (MR). Informat

恩XP

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

文件：58.08 Kbytes 页数：5 Pages

PHI

飞利浦

Dual 4-bit static shift register

1. General description The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR)

文件：213.5 Kbytes 页数：11 Pages

NEXPERIA

安世