丝印：ABT2827；Package：SOIC；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Output Ports Have Equivalent 25-W Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical

文件：301.69 Kbytes 页数：12 Pages

TI

德州仪器

丝印：ABT2827；Package：SOIC；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Output Ports Have Equivalent 25-W Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical

文件：301.69 Kbytes 页数：12 Pages

TI

德州仪器

丝印：ABT2827；Package：SOIC；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Output Ports Have Equivalent 25-W Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical

文件：301.69 Kbytes 页数：12 Pages

TI

德州仪器

丝印：ABT2827；Package：SOIC；10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Output Ports Have Equivalent 25-W Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical

文件：301.69 Kbytes 页数：12 Pages

TI

德州仪器