Hex Schmitt?뭈rigger Inverter with LSTTL Compatible Inputs High?뭁erformance Silicon?묰ate CMOS

Hex Schmitt−Trigger Inverter with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The 74HCT14 may be used as a level converter for interfacing TTL or NMOS outputs to high−speed CMOS inputs. The HCT14 is useful to “square up” slow input rise and fall times. Due to the hysteresis volta

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ONSEMI

安森美半导体

Hex inverting Schmitt trigger

DESCRIPTION The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of tr

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PHI

PHI

Hex inverting Schmitt trigger

DESCRIPTION The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of tr

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PHI

PHI

HEX INVERTERS WITH SCHMITT TRIGGER INPUTS

Description The 74HCT14 provides provides six independent Schmitt trigger input inverters with standard push-pull outputs. The device is designed for operation with a power supply range of 4.5V to 5.5V. Features • Wide Supply Voltage Range from 4.5V to 5.5V • Pin Compatible with Low Power Scho

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DIODES

美台半导体

10-TO-4 LINE PRIORITY ENCODER

GENERAL DESCRIPTION The 74HC/HCT147 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Encodes 10-line decimal to 4-line BCD • Useful for 10-position switch encoding • Used in

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PHI

PHI

10-to-4 line priority encoder

GENERAL DESCRIPTION The 74HC/HCT147 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Encodes 10-line decimal to 4-line BCD • Useful for 10-position switch encoding • Used in

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PHI

PHI

10-TO-4 LINE PRIORITY ENCODER

GENERAL DESCRIPTION The 74HC/HCT147 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Encodes 10-line decimal to 4-line BCD • Useful for 10-position switch encoding • Used in

文件：43.55 Kbytes 页数：7 Pages

PHI

PHI

Hex inverting Schmitt trigger

1. General description The 74HC14; 74HCT14 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to vol

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NEXPERIA

安世

Hex inverting Schmitt trigger

DESCRIPTION The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of tr

文件：120.59 Kbytes 页数：23 Pages

PHI

PHI

Hex inverting Schmitt trigger

1. General description The 74HC14-Q100; 74HCT14-Q100 is a hex inverter with Schmitt-trigger inputs. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inp

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NEXPERIA

安世