3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

文件：274.63 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138-Q100; 74HCT138-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This m

文件：273.19 Kbytes 页数：15 Pages

NEXPERIA

安世

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Grade 1) ◆ Specified from -40 °C to +85 °C and from -40 °

文件：241.85 Kbytes 页数：18 Pages

恩XP

3-to-8 line decoder/demultiplexer; inverting

General description The 74HC138-Q100; 74HCT138-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Grade 1) ◆ Specified from -40 °C to +85 °C and from -40 °

文件：241.85 Kbytes 页数：18 Pages

恩XP

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

文件：243.29 Kbytes 页数：13 Pages

NEXPERIA

安世

Dual 2-to-4 line decoder/demultiplexer

General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4

文件：156.99 Kbytes 页数：17 Pages

恩XP

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

文件：44.7 Kbytes 页数：7 Pages

PHI

PHI

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

文件：44.7 Kbytes 页数：7 Pages

PHI

PHI

Dual 2-to-4 line decoder/demultiplexer

General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4

文件：156.99 Kbytes 页数：17 Pages

恩XP

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

文件：243.29 Kbytes 页数：13 Pages

NEXPERIA

安世