Triple 3-input NAND gate

1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand

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安世

Triple 3-input NAND gate

1. General description The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) stand

文件：223.95 Kbytes 页数：11 Pages

NEXPERIA

安世

Triple 3-input AND gate

GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. FEATURES • Output capability: standard • ICC categor

文件：33.63 Kbytes 页数：5 Pages

PHI

飞利浦

Triple 3-input AND gate

General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC11; 74HCT11 provides a triple 3-input AND function. Features ■ Input levels: ◆ For 74HC11: CMOS level

文件：327.04 Kbytes 页数：15 Pages

恩XP

Triple 3-input AND gate

1. General description The 74HC11; 74HCT11 is a triple 3-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power di

文件：229.08 Kbytes 页数：11 Pages

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High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Bus Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS112.

文件：295.3 Kbytes 页数：6 Pages

SS

Dual JK flip-flop with set and reset; negative-edge trigger

1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen

文件：267.28 Kbytes 页数：16 Pages

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安世

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

文件：106.77 Kbytes 页数：15 Pages

PHI

飞利浦

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Bus Drive Capability: 15 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS112.

文件：295.3 Kbytes 页数：6 Pages

SS

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

文件：106.77 Kbytes 页数：15 Pages

PHI

飞利浦