Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

PHI

Quad buffer/line driver; 3-state

General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to inter

文件：41.7 Kbytes 页数：6 Pages

恩XP

HCMOS family characteristics

文件：87.96 Kbytes 页数：19 Pages

PHI

PHI

4-bit magnitude comparator

文件：73.56 Kbytes 页数：9 Pages

PHI

PHI

4-bit binary full adder with fast carry

FEATURES · High-speed 4-bit binary addition · Cascadable in 4-bit increments · Fast internal look-ahead carry · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT283 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LST

文件：65.51 Kbytes 页数：8 Pages

PHI

PHI

Dual retriggerable precision monostable multivibrator

GENERAL DESCRIPTION The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Separate reset inputs • Triggering from leading or trailing edge • Output capa

文件：149.94 Kbytes 页数：13 Pages

PHI

PHI

Octal bus transceiver; 3-state

GENERAL DESCRIPTIONS The 74HC/HCT245 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Octal bidirectional bus interface • Non-inverting 3-state outputs • Output c

文件：130.69 Kbytes 页数：22 Pages

PHI

PHI

Octal bus transceiver; 3-state

GENERAL DESCRIPTIONS The 74HC/HCT245 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Octal bidirectional bus interface • Non-inverting 3-state outputs • Output c

文件：130.69 Kbytes 页数：22 Pages

PHI

PHI

Quad 2-input NAND gate

DESCRIPTION The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00/74HCT00 provide the 2-input NAND function. FEATURES • Complies with JEDEC standard no. 8-1A •

文件：28.03 Kbytes 页数：5 Pages

PHI

PHI

Quad 2-Input NAND Gate High-Performance Silicon-Gate CMOS

Quad 2-Input NAND Gate High−Performance Silicon−Gate CMOS The MC74HC00A is identical in pinout to the LS00. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive Capability: 10 LSTTL Loads • Output

文件：110.23 Kbytes 页数：7 Pages

ONSEMI

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