Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock inp

文件：259.39 Kbytes 页数：15 Pages

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安世

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

文件：271.64 Kbytes 页数：16 Pages

NEXPERIA

安世

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109.

文件：303.58 Kbytes 页数：6 Pages

SS

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS109.

文件：303.58 Kbytes 页数：6 Pages

SS

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

文件：271.64 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and

文件：257.709 Kbytes 页数：16 Pages

NEXPERIA

安世

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦