Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

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FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

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PHI

飞利浦

Triple 3-Input AND Gate

文件：64.269 Kbytes 页数：5 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Triple 3-Input AND Gate

ONSEMI

安森美半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

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FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

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PHI

飞利浦

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as lo

文件：59.83 Kbytes 页数：6 Pages

FairchildFairchild Semiconductor

仙童半导体飞兆/仙童半导体公司