Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Package：16-DIP（0.300"，7.62mm）；包装：袋 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16DIP

ONSEMI

安森美半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体