Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

文件：83.94 Kbytes 页数：10 Pages

PHI

PHI

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

丝印：74F112；Package：SOP；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 页数：16 Pages

TI

德州仪器

丝印：74F112；Package：SOP；DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of t

文件：566.64 Kbytes 页数：16 Pages

TI

德州仪器

Dual JK Negative Edge-Triggered Flip-Flop

ONSEMI

安森美半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体