ZL30120中文资料SONET/SDH Line Card System Synchronizer数据手册Microchip规格书

描述 Description

The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.Click here for secure documentation

特性 Features

Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.813, and compatible with ITU-T G.8261 (formerly G.pactiming)
Internal low jitter APLL provides SONET/SDH clocks including 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz, or 25 MHz and 50 MHz Synchronous Ethernet output clocks
Provides two DPLLs which have independent modes of operation (locked, free-run, holdover) and optional hitless reference switching
Programmable output synthesizers (P0, P1) generate general purpose clock frequencies from any multiple of 8 kHz up to 100 MHz
Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to output phase alignment
Typical Applications
AMCs for AdvancedTCATMand MicroTCA
Systems
Synchronous Ethernet
Multi-Service Edge Switches or Routers
DSLAM Line Cards
WAN Line Cards RNC/Mobile Switching Center Line Cards
ADM Line Cards

简介

ZL30120属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30120应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。