CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

文件：109.33 Kbytes 页数：9 Pages

INTERSIL

CMOS NAND GATES

文件：525.82 Kbytes 页数：13 Pages

TI

德州仪器

Dual 4-Input NOR(NAND) Gate

文件：113.28 Kbytes 页数：6 Pages

NSC

国半

Dual 4-Input NOR(NAND) Gate

文件：107.87 Kbytes 页数：6 Pages

NSC

国半

4路输入非门

4路输入非门,工作电压（Vcc）(v)3-15V,静态电流Iq(Typ)0.01uA

XBLW

芯伯乐

2路4输入与非门

The CD4012 is a Dual 4-input Nand Gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to GND (usually ground). Unused inputs must be connected to VDD, GND, or a • Wide supply voltage range from 3V to 15V\n• Fully static operation\n• 5V, 10V, and 15V parametric ratings\n• Standardized symmetrical output characteristics\n• Inputs and outputs are protected against electrostatic effects\n• Specified from -40℃ to +125℃\n• Packaging information: DIP14/SOP14/TSSOP;

I-CORE

中微爱芯

CMOS NAND Gates

Renesas

瑞萨

CMOS NAND Gates

Features: Quiescent current specified to 15 V Maximum input leakage of 1 uA at 15 V (full package-temperature range) 1-V noise margin (full package-temperature range)

文件：550.23 Kbytes 页数：10 Pages

TI

德州仪器

CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4012BE；Package：PDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器