首页 >CD4012>规格书列表

型号下载 订购功能描述制造商 上传企业LOGO

CD4012

CMOS NAND Gates

Description CD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 I

文件:109.33 Kbytes 页数:9 Pages

Intersil

CD4012

CMOS NAND GATES

文件:525.82 Kbytes 页数:13 Pages

TI

德州仪器

CD4012

Dual 4-Input NOR(NAND) Gate

文件:113.28 Kbytes 页数:6 Pages

NSC

国半

CD4012

Dual 4-Input NOR(NAND) Gate

文件:107.87 Kbytes 页数:6 Pages

NSC

国半

CD4012BE

丝印:CD4012BE;Package:PDIP;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件:1.0201 Mbytes 页数:23 Pages

TI

德州仪器

CD4012BE.A

丝印:CD4012BE;Package:PDIP;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件:1.0201 Mbytes 页数:23 Pages

TI

德州仪器

CD4012BEE4

丝印:CD4012BE;Package:PDIP;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件:1.0201 Mbytes 页数:23 Pages

TI

德州仪器

CD4012BF3A

丝印:CD4012BF3A;Package:CDIP;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件:1.0201 Mbytes 页数:23 Pages

TI

德州仪器

CD4012BF3A.A

丝印:CD4012BF3A;Package:CDIP;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件:1.0201 Mbytes 页数:23 Pages

TI

德州仪器

CD4012BM

丝印:CD4012BM;Package:SOIC;CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件:1.0201 Mbytes 页数:23 Pages

TI

德州仪器

技术参数

  • Function:

    NAND gates

  • Description:

    Dual 4-input NAND gate

  • VCC (V):

    3.0 - 15.0

  • Logic switching levels:

    CMOS

  • Tamb (°C):

    -40~125

  • Nr of pins:

    14

  • Package:

    DIP14/SOP14/TSSOP14

供应商型号品牌批号封装库存备注价格
24+
4
询价
ST
24+
SMD
20000
一级代理原装现货假一罚十
询价
ST/TI
25+23+
TO-220
25716
绝对原装正品全新进口深圳现货
询价
ST/意法
24+
DIP
300
大批量供应优势库存热卖
询价
ST/意法
23+
DIP
8215
原厂原装
询价
HLF/洪利发
23+
DIPSOP
35000
询价
TI(德州仪器)
24+
NA/
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
HLF/洪利发
24+
NA/
38250
原装现货,当天可交货,原型号开票
询价
PHI/ST/TI
23+
DIP/SOP
7300
专注配单,只做原装进口现货
询价
HLF/洪利发
24+
DIPSOP
60000
全新原装现货
询价
更多CD4012供应商 更新时间2025-12-24 16:30:00