丝印：CD4012BF3A；Package：CDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

丝印：CD4012BF3A；Package：CDIP；CMOS NAND GATES

Features: Propagation delay time = 60 ns (typ.) at CL =50 pF, Vpp = 10V = Buffered inputs and outputs = Standardized symmetrical output characteristics Maximum input current of 1 uA at 18 V over full package temperature range; 100 nA at 18 V and 25°C = 100% tested for quiescent curre

文件：1.0201 Mbytes 页数：23 Pages

TI

德州仪器

CMOS NAND GATES

文件：525.82 Kbytes 页数：13 Pages

TI

德州仪器

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages

文件：523.01 Kbytes 页数：12 Pages

TI

德州仪器

CMOS NAND GATES

文件：1.18484 Mbytes 页数：19 Pages

TI

德州仪器

CMOS NAND GATES

文件：1.29026 Mbytes 页数：20 Pages

TI

德州仪器

CMOS NAND GATES

文件：1.18484 Mbytes 页数：19 Pages

TI

德州仪器