8-bit shift register with input latches

GENERAL DESCRIPTION The 74HC/HCT7597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT7597 both consist of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit sh

文件：90.25 Kbytes 页数：12 Pages

PHI

PHI

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：57.41 Kbytes 页数：7 Pages

PHI

PHI

Quad bistable transparant latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：87.52 Kbytes 页数：20 Pages

恩XP

Quad bistable transparant latch

1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs foll

文件：257.81 Kbytes 页数：16 Pages

NEXPERIA

安世

Quad bistable transparant latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：87.52 Kbytes 页数：20 Pages

恩XP

Quad bistable transparant latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：87.52 Kbytes 页数：20 Pages

恩XP

Quad bistable transparant latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：87.52 Kbytes 页数：20 Pages

恩XP

Quad bistable transparant latch

1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs foll

文件：257.81 Kbytes 页数：16 Pages

NEXPERIA

安世

Quad bistable transparant latch

文件：113.52 Kbytes 页数：20 Pages

PHI

PHI

Octal Schmitt trigger buffer/line driver; 3-state

文件：554.29 Kbytes 页数：17 Pages

恩XP