74HC75PW集成电路（IC）的锁存器规格书PDF中文资料

74HC75PW属于集成电路（IC）的锁存器。由安世半导体(中国)有限公司制造生产的74HC75PW锁存器锁存器是类似于触发器的基本数字存储设备，但是不同之处在于，在锁存使能（或类似命名）信号处于有效逻辑状态的任何时间，保持的逻辑状态都可以改变。“透明”锁存器还允许设备输出在锁存使能信号有效时反映输入的当前状态，而相反的是，状态仅在保持状态已固定时改变。

1. General description

The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are

simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn

is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data

inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior

to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain

stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current

limiting resistors to interface inputs to voltages in excess of VCC.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 6.0 V

• CMOS low power dissipation

• High noise immunity

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8C (2.7 V to 3.6 V)

• JESD7A (2.0 V to 6.0 V)

• Complementary Q and Q outputs

• VCC and GND on the center pins

• CMOS input levels

• ESD protection:

• HBM EIA/JESD22-A114F exceeds 2000 V

• MM EIA/JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +80 °C and from -40 °C to +125 °C.