Quad bistable transparant latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

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Quad bistable transparant latch

1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs foll

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Quad bistable transparent latch

The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as l • Complementary Q and Q outputs\n• VCC and GND on the center pins\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC75: CMOS level\n\n• ESD protection:• HBM EIA/JESD22-A114F exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• ;

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Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 锁存器 描述：IC LATCH QUAD BISTABLE 16TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 锁存器 描述：IC LATCH QUAD BISTABLE 16TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司