Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：57.41 Kbytes 页数：7 Pages

PHI

飞利浦

Quad bistable transparant latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

文件：87.52 Kbytes 页数：20 Pages

恩XP

Quad bistable transparant latch

1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs foll

文件：257.81 Kbytes 页数：16 Pages

NEXPERIA

安世

Quad bistable transparant latch

Features n Complementary Q and Q outputs n VCC and GND on the center pins n Low-power dissipation n Complies with JEDEC standard no. 7A n ESD protection: u HBM EIA/JESD22-A114-B exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V. n Multiple package options n Specified from -40 °C to +80

文件：148.71 Kbytes 页数：20 Pages

SOLIDSTATE

Octal Schmitt trigger buffer/line driver; 3-state; inverting

1. General description The 74HC7540; 74HCT7540 is an 8-bit inverting buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This

文件：270.29 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal Schmitt trigger buffer/line driver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT7540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Schmitt trigger action on all data inputs • Output capab

文件：55.96 Kbytes 页数：7 Pages

PHI

飞利浦

Octal Schmitt trigger buffer/line driver; 3-state; inverting Rev. 4 ??31 December 2012

General description The 74HC7540; 74HCT7540 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. Features and benefits ■ Inverting outputs ■ Low-power dissipation ■ ESD protection: ◆ HBM J

文件：157.28 Kbytes 页数：16 Pages

恩XP

Octal Schmitt trigger buffer/line driver; 3-state; inverting Rev. 4 ??31 December 2012

General description The 74HC7540; 74HCT7540 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. Features and benefits ■ Inverting outputs ■ Low-power dissipation ■ ESD protection: ◆ HBM J

文件：157.28 Kbytes 页数：16 Pages

恩XP

Octal Schmitt trigger buffer/line driver; 3-state; inverting

1. General description The 74HC7540; 74HCT7540 is an 8-bit inverting buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This

文件：270.29 Kbytes 页数：15 Pages

NEXPERIA

安世

Octal Schmitt trigger buffer/line driver; 3-state; inverting

1. General description The 74HC7540; 74HCT7540 is an 8-bit inverting buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This

文件：270.29 Kbytes 页数：15 Pages

NEXPERIA

安世