丝印：74HC4049D；Package：SOIC16；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Hex Buffer 74HC4049D: HEX BUFFER/CONVERTER (INVERTING) 74HC4050D: HEX BUFFER/CONVERTER General The 74HC4049D and 74HC4050D are high speed CMOS HEX BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTT

文件：205.58 Kbytes 页数：8 Pages

TOSHIBA

东芝

High Speed CMOS Logic

Features  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1μA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with CD4040B

文件：1.16094 Mbytes 页数：7 Pages

SS

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

文件：275.04 Kbytes 页数：16 Pages

NEXPERIA

安世

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

飞利浦

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

飞利浦

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

文件：275.04 Kbytes 页数：16 Pages

NEXPERIA

安世

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

文件：275.04 Kbytes 页数：16 Pages

NEXPERIA

安世

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

飞利浦

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

飞利浦

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

飞利浦