Hex inverting HIGH-to-LOW level shifter

1. General description The 74HC4049 is a hex inverter with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Overvolta

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Hex inverting high-to-low level shifter

GENERAL DESCRIPTION The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the “4049” of the “4000B” series. It is specified in compliance with JEDEC standard no. 7A. The 74HC4049 provides six inverting buffers with a modified input protection structure, which has no diode c

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Hex inverting HIGH-to-LOW level shifter

1. General description The 74HC4049 is a hex inverter with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Overvolta

文件：221.33 Kbytes 页数：11 Pages

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12-stage binary ripple counter

文件：762.31 Kbytes 页数：19 Pages

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12-stage binary ripple counter

文件：762.31 Kbytes 页数：19 Pages

NEXPERIA

安世

12-stage binary ripple counter

文件：762.31 Kbytes 页数：19 Pages

NEXPERIA

安世

12-stage binary ripple counter

文件：762.31 Kbytes 页数：19 Pages

NEXPERIA

安世

12-stage binary ripple counter

文件：762.31 Kbytes 页数：19 Pages

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12-stage binary ripple counter

The 74HC4040-Q100; 74HCT4040-Q100 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all o • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C\n\n• Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC4040-Q100: CMOS level\n• For 74HCT4040-Q100: TTL level\n\n• ESD protection:• MIL-STD-883, method 301;

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12-stage binary ripple counter

The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC4040: CMOS level\n• For 74HCT4040: TTL level\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C;

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