12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

PHI

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

PHI

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages

文件：160.9 Kbytes 页数：18 Pages

恩XP

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

PHI

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

PHI

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages

文件：160.9 Kbytes 页数：18 Pages

恩XP

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

文件：275.04 Kbytes 页数：16 Pages

NEXPERIA

安世

Phase-Locked Loop

The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC4046 phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op amp DEMOUT. The comparators have two common sig

文件：134.42 Kbytes 页数：12 Pages

SLS

CMOS Phase Lock Loop

General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and t

文件：250.91 Kbytes 页数：17 Pages

FAIRCHILD

仙童半导体

Phase-Locked Loop

Phase−Locked Loop High−Performance Silicon−Gate CMOS The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive Cap

文件：290.13 Kbytes 页数：16 Pages

ONSEMI

安森美半导体