Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

文件：58.4 Kbytes 页数：8 Pages

PHI

PHI

丝印：74HC273D；Package：SOIC20；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Octal D-Type Flip-Flop with Clear General The 74HC273D is a high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Infor

文件：207.58 Kbytes 页数：12 Pages

TOSHIBA

东芝

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

文件：279.81 Kbytes 页数：17 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

文件：58.4 Kbytes 页数：8 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

文件：277.13 Kbytes 页数：18 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

文件：58.4 Kbytes 页数：8 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

文件：58.4 Kbytes 页数：8 Pages

PHI

PHI

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

文件：279.81 Kbytes 页数：17 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

文件：277.13 Kbytes 页数：18 Pages

NEXPERIA

安世

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the

文件：277.13 Kbytes 页数：18 Pages

NEXPERIA

安世