74HC27

High Speed CMOS Logic

Features OutputDriveCapability:10LSTTLLoads LowInputCurrent:1μA OutputsdirectlyinterfaceCMOS,NMOSandTTL OperatingVoltageRange:2Vto6V Functioncompatiblewith54LS27 HighNoiseImmunityCMOSprocess.

74HC27

Triple 3-input NOR gate

GENERALDESCRIPTION The74HC/HCT27arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. The74HC/HCT27providethe3-inputNORfunction. FEATURES •Outputcapability:standard •ICCcategor

74HC27

Triple 3-input NOR gate

74HC273

Octal D-type flip-flop with reset; positive-edge trigger

Generaldescription The74HC273;74HCT273isanoctalpositive-edgetriggeredD-typeflip-flop.Thedevicefeaturesclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethestateoftheircorrespondingDninputsthatmeettheset-upandholdtimerequirementsontheLOW-to-HIGHc

74HC273

Octal D Flip-Flop with Common Clock and Reset

TheSL74HC273isidenticalinpinouttotheLS/ALS273.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLS/ALSTTLoutputs.ThisdeviceconsistsofeightDflip-flopswithcommonClockandResetinputs.Eachflip-flopisloadedwithalow-

74HC273

Octal D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC273;74HCT273isanoctalpositive-edgetriggeredD-typeflip-flop.Thedevice featuresclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethestateoftheir correspondingDninputsthatmeettheset-upandholdtimerequirementsontheLOW-to-HIG

74HC273A

Octal D Flip-Flop with Common Clock and Reset

OctalDFlip-FlopwithCommonClockandReset High−PerformanceSilicon−GateCMOS TheMC74HC273AisidenticalinpinouttotheLS273.ThedeviceinputsarecompatiblewithstandardCMOSoutputs;withpullupresistors,theyarecompatiblewithLSTTLoutputs. ThisdeviceconsistsofeightDflip−f

74HC273BQ

Octal D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC273;74HCT273isanoctalpositive-edgetriggeredD-typeflip-flop.Thedevice featuresclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethestateoftheir correspondingDninputsthatmeettheset-upandholdtimerequirementsontheLOW-to-HIG

74HC273BQ-Q100

Octal D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC273-Q100;74HCT273-Q100isanoctalpositive-edgetriggeredD-typeflip-flop.The devicefeaturesclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethe stateoftheircorrespondingDninputsthatmeettheset-upandholdtimerequirementsonthe

74HC273D

Octal D-type flip-flop with reset; positive-edge trigger

Generaldescription The74HC273;74HCT273isanoctalpositive-edgetriggeredD-typeflip-flop.Thedevicefeaturesclock(CP)andmasterreset(MR)inputs.TheoutputsQnwillassumethestateoftheircorrespondingDninputsthatmeettheset-upandholdtimerequirementsontheLOW-to-HIGHc