Triple 3-input NOR gate

GENERAL DESCRIPTION The 74HC/HCT27 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT27 provide the 3-input NOR function. FEATURES • Output capability: standard • ICC categor

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PHI

飞利浦

Triple 3-input NOR gate

General description The 74HC27; 74HCT27 is a triple 3-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits ■ Complies with JEDEC standard no. 7A ■ Input levels: ◆ For 74HC27:

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恩XP

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V Function compatible with 54LS27 High Noise Immunity CMOS process.

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SS

Triple 3-input NOR gate

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NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

丝印：74HC273D；Package：SOIC20；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Octal D-Type Flip-Flop with Clear General The 74HC273D is a high speed CMOS OCTAL D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Infor

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TOSHIBA

东芝

Octal D-type flip-flop with reset; positive-edge trigger

General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH c

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PHI

飞利浦

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

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NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Octal D Flip-Flop with Common Clock and Reset

The SL74HC273 is identical in pinout to the LS/ALS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-

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SLS

Octal D Flip-Flop with Common Clock and Reset

Octal D Flip-Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS The MC74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip−f

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ONSEMI

安森美半导体

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIG

文件：279.81 Kbytes 页数：17 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司