74HC137

3-to-8 line decoder, demultiplexer with address latches; inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to

74HC137

3-to-8 line decoder/demultiplexer with address latches; inverting

GENERALDESCRIPTION The74HC/HCT137arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES •Combines3-to-8decoderwith3-bitlatch •Multipleinputenableforeasyexpansionorind

74HC137

3-to-8 line decoder, demultiplexer with address latches inverting

74HC137

3-to-8 line decoder/demultiplexer with address latches; inverting

74HC137D

3-to-8 line decoder, demultiplexer with address latches; inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to

74HC137D

3-to-8 line decoder, demultiplexer with address latches; inverting; • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM EIA/JESD22-A114-B exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n\n• Specified from -40 °C to +80 °C and from -40 °C to +125 °C\n;

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.\n The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH.\n The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.\n The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.\n

74HC137DB

3-to-8 line decoder, demultiplexer with address latches; inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to

74HC137DB

3-to-8 line decoder, demultiplexer with address latches; inverting; • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM EIA/JESD22-A114-B exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n\n• Specified from -40 °C to +80 °C and from -40 °C to +125 °C\n;

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.\n The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH.\n The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.\n The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.\n

74HC137PW

3-to-8 line decoder, demultiplexer with address latches; inverting; • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Wide supply voltage range from 2.0 to 6.0 V\n• CMOS low power dissipation\n• High noise immunity\n• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B\n• Complies with JEDEC standards• JESD8C (2.7 V to 3.6 V)\n• JESD7A (2.0 V to 6.0 V)\n\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Specified from -40 °C to +80 °C and from -40 °C to +125 °C.\n;

The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores the data that was present before the transition in the latches. Further address changes are ignored as long as LE remains HIGH.\n The output enable inputs control the state of the outputs independently of the address inputs or latch operation. All outputs will be HIGH unless E1 is LOW and E2 is HIGH.\n Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC137PW

3-to-8 line decoder, demultiplexer with address latches; inverting

1.Generaldescription The74HC137decodesthreebinaryweightedaddressinputs(A0,A1andA2)toeightmutually exclusiveoutputs(Y0toY7).Thedevicefeaturesalatchenable(LE)andtwooutputenable(E1, E2)inputs.ALOWonLEcausesthedevicetoactasanactiveLOWdecoder.ALOW-to