3-to-8 line decoder, demultiplexer with address latches; inverting

The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Wide supply voltage range from 2.0 to 6.0 V\n• CMOS low power dissipation\n• High noise immunity\n• Latch-up performance exceeds 100 mA per JESD ;

Nexperia

安世

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

文件：273.83 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 信号开关，多路复用器，解码器 描述：IC DECODER/DEMUX 1X3:8 16TSSOP

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes 页数：10 Pages

TI

德州仪器

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：381.06 Kbytes 页数：16 Pages

TI

德州仪器

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：528.3 Kbytes 页数：19 Pages

TI

德州仪器