74HC137PW中文资料3-to-8 line decoder, demultiplexer with address latches; inverting数据手册Nexperia规格书

描述 Description

The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores the data that was present before the transition in the latches. Further address changes are ignored as long as LE remains HIGH.
The output enable inputs control the state of the outputs independently of the address inputs or latch operation. All outputs will be HIGH unless E1 is LOW and E2 is HIGH.
Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

特性 Features

• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active LOW mutually exclusive outputs
• Wide supply voltage range from 2.0 to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)

• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +80 °C and from -40 °C to +125 °C.