Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

文件：48.31 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

文件：48.31 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Triple 3-Input NAND Gate

General Description This device contains three independent gates, each of which performs the logic NAND function.

文件：48.31 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

文件：48.32 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

文件：72.11 Kbytes 页数：8 Pages

PHI

PHI

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

文件：83.94 Kbytes 页数：10 Pages

PHI

PHI

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

文件：59.07 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体