8-Bit Schottky Barrier Diode Array

General Description The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features ■ 8-Bit a

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8-Bit Schottky Barrier Diode Array

General Description The 74F1056 is an 8-bit Schottky barrier diode array designed to be employed as termination on the inputs to memory bus lines or CLOCK lines. This device is designed to suppress negative transients caused by line reflections, switching noise and crosstalk. Features ■ 8-Bit a

文件：35.39 Kbytes 页数：4 Pages

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18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

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18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

文件：91.83 Kbytes 页数：6 Pages

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18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

文件：91.83 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

18-Bit Undershoot/Overshoot Clamp

General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at

文件：91.83 Kbytes 页数：6 Pages

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Positive J-K positive edge-triggered flip-flops

DESCRIPTION The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are

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PHI

PHI

Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

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Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

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Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

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