Dual JK Positive Edge-Triggered Flip-Flop

General Description The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J

文件：79.72 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Dual JK Positive Edge-Triggered Flip-Flop

文件：80.64 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop

文件：384.64 Kbytes 页数：12 Pages

TI

德州仪器

Dual JK Positive Edge-Triggered Flip-Flop

文件：133.12 Kbytes 页数：10 Pages

NSC

国半

Package：16-DIP（0.300"，7.62mm）；包装：袋 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF JK TYPE DUAL 1BIT 16DIP

ONSEMI

安森美半导体