71V65703数据手册集成电路（IC）的存储器规格书PDF

描述 Description

The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register).In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

特性 Features

High performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages