71V65603中文资料3.3V 256K X 36 ZBT Synchronous 3.3V I/O PipeLined SRAM数据手册Renesas规格书

描述 Description

The 71V656033.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers.In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

特性 Features

High performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read cycles
Internally synchronized output buffer enable eliminates the need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (VDDQ)
Power down controlled by ZZ input
Available in 100-pin TQFP, 119-pin BGA and 165 fpBGA packages