Silicon NPN triple diffusion mesa type(For horizontal deflection output)

For horizontal deflection output ■ Features ● High breakdown voltage, and high reliability through the use of a glass passivation layer ● High-speed switching ● Wide area of safe operation (ASO)

文件：35 Kbytes 页数：2 Pages

PANASONIC

松下

ACT5270 64-Bit Superscaler Microprocessor

DESCRIPTION The ACT5270 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory

文件：160.93 Kbytes 页数：5 Pages

AEROFLEX

丝印：527R02ILF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features • Packaged as 28-pin SSOP, Pb-free (150 mil body) • Synchronizes fractional clocks rising edges • PECL IN to CMOS OUT • Pin selectable dividers • Zero input to output skew • User determines the output frequency—no software needed • Slices frequency or period • Input clock frequen

文件：374.35 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：527R02ILF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features • Packaged as 28-pin SSOP, Pb-free (150 mil body) • Synchronizes fractional clocks rising edges • PECL IN to CMOS OUT • Pin selectable dividers • Zero input to output skew • User determines the output frequency—no software needed • Slices frequency or period • Input clock frequen

文件：374.35 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：527R02LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features • Packaged as 28-pin SSOP, Pb-free (150 mil body) • Synchronizes fractional clocks rising edges • PECL IN to CMOS OUT • Pin selectable dividers • Zero input to output skew • User determines the output frequency—no software needed • Slices frequency or period • Input clock frequen

文件：374.35 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：527R02LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

Features • Packaged as 28-pin SSOP, Pb-free (150 mil body) • Synchronizes fractional clocks rising edges • PECL IN to CMOS OUT • Pin selectable dividers • Zero input to output skew • User determines the output frequency—no software needed • Slices frequency or period • Input clock frequen

文件：374.35 Kbytes 页数：11 Pages

RENESAS

瑞萨

丝印：527R-03LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB

Features • Packaged as 28 pin SSOP, Pb free (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Input clock frequ

文件：365.1 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：527R-03LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB

Features • Packaged as 28 pin SSOP, Pb free (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Input clock frequ

文件：365.1 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：527R-04LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

Features • Packaged as 28-pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • PECL in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Inp

文件：379.45 Kbytes 页数：10 Pages

RENESAS

瑞萨

丝印：527R-04LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB

Features • Packaged as 28-pin SSOP (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • PECL in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Inp

文件：379.45 Kbytes 页数：10 Pages

RENESAS

瑞萨