527R-02ILF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

• Packaged as 28-pin SSOP, Pb-free (150 mil body)

• Synchronizes fractional clocks rising edges

• PECL IN to CMOS OUT

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency—no software

needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz to 200 MHz

• Output clock frequencies from 4 MHz to 160 MHz

• Very low jitter

• Duty cycle of 45/55

• Operating voltage of 3.3 V

• Advanced, low-power CMOS process

• Industrial temperature version available