丝印：527R-03LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB

Features • Packaged as 28 pin SSOP, Pb free (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Input clock frequ

文件：365.1 Kbytes 页数：10 Pages

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瑞萨

丝印：527R-03LF；Package：SSOP；CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB

Features • Packaged as 28 pin SSOP, Pb free (150 mil body) • Synchronizes fractional clocks rising edges • CMOS in to PECL out • Pin selectable dividers • Zero input to output skew • User determines the output frequency - no software needed • Slices frequency or period • Input clock frequ

文件：365.1 Kbytes 页数：10 Pages

RENESAS

瑞萨

Clock Slicer User Configurable PECL Output Zero Delay Buffer

Description The ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divi

文件：166 Kbytes 页数：8 Pages

ICST

Clock Slicer User Configurable PECL Output Zero Delay Buffer

Description The ICS527-03 is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divi

文件：166 Kbytes 页数：8 Pages

ICST