| 型号 | 下载 订购 | 功能描述 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat 文件：895.31 Kbytes 页数：55 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat 文件：895.31 Kbytes 页数：55 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat 文件：895.31 Kbytes 页数：55 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat 文件：895.31 Kbytes 页数：55 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat 文件：895.31 Kbytes 页数：55 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
4/8/16 Port IMA/TC PHY Device Description The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilizat 文件：895.31 Kbytes 页数：55 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
T1/E1 Synchronizer Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces 文件：424.09 Kbytes 页数：27 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by 文件：650.4 Kbytes 页数：38 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by 文件：650.4 Kbytes 页数：38 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK | ||
SONET/SDH System Synchronizer Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by 文件：650.4 Kbytes 页数：38 Pages | ZARLINK Zarlink Semiconductor Inc | ZARLINK |
技术参数
- DPLLs or Paths：
1
- DPLL Bandwidth (Hz)：
1.9
- Inputs：
2
- Diff Outputs：
0
- CMOS Outputs：
6
- Low-Jitter Synthesizers：
0
- General Purpose Synthsizers：
0
- Typical Jitter (12kHz-20MHz) fs RMS：
Stratum 3
- Diff InputFreq Range：
1.544 MHz
- Output Freq Range：
16.384 MHz
- NV Memory：
N/A
- NCO ppb：
N/A
- Align：
3
- Packages：
Please call for package information
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Altech Corp. |
2022+ |
103 |
全新原装 货期两周 |
询价 | |||
ZARLINK |
1637+ |
SSOP24 |
210 |
全新原装现货 |
询价 | ||
APTINA |
24+ |
QFN |
598000 |
原装现货假一赔十 |
询价 | ||
multitech |
25+ |
模块板 |
13 |
旗舰店 |
询价 | ||
MAGNTEK |
22+ |
TO94 |
30000 |
价格优惠,欢迎咨询 |
询价 | ||
onsemi(安森美) |
2021+ |
- |
499 |
询价 | |||
MICROCHIP |
23+ |
PLCC-28 |
10000 |
公司只做原装，可来电咨询 |
询价 | ||
ZARLINK |
25+ |
10000 |
全新原装现货库存 |
询价 | |||
AEROSEMI |
250 |
询价 | |||||
MITEL |
26+ |
原厂原封装 |
86720 |
代理授权原装正品价格最实惠 本公司承诺假一赔百 |
询价 |
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