Quad bus buffer (3-state)

Features • High-speed: tPD = 8 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIL = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 6 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating vo

文件：510.65 Kbytes 页数：14 Pages

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3 TO 8 LINE DECODER/LATCH

DESCRIPTION The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

文件：262.65 Kbytes 页数：12 Pages

STMICROELECTRONICS

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3 TO 8 LINE DECODER/LATCH

DESCRIPTION The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

文件：262.65 Kbytes 页数：12 Pages

STMICROELECTRONICS

意法半导体

3 TO 8 LINE DECODER/LATCH

DESCRIPTION The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

文件：262.65 Kbytes 页数：12 Pages

STMICROELECTRONICS

意法半导体

3 TO 8 LINE DECODER/LATCH

DESCRIPTION The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

文件：262.65 Kbytes 页数：12 Pages

STMICROELECTRONICS

意法半导体

3 TO 8 LINE DECODER/LATCH

DESCRIPTION The M54/74HC131 is a high speed CMOS 3 TO 8 LINE DECODER/LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

文件：262.65 Kbytes 页数：12 Pages

STMICROELECTRONICS

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QUAD 2-INPUT SCHMITT NAND GATE

DESCRIPTION The M54/74HC132 is a high speed CMOSQUAD2-INPUT SCHMITT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Pin configuration and function are identical to those of the M54/74HC00.

文件：234.94 Kbytes 页数：9 Pages

STMICROELECTRONICS

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QUAD 2-INPUT SCHMITT NAND GATE

DESCRIPTION The M54/74HC132 is a high speed CMOSQUAD2-INPUT SCHMITT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Pin configuration and function are identical to those of the M54/74HC00.

文件：180.38 Kbytes 页数：9 Pages

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Quad 2-input Schmitt NAND gate

Features • High-speed: tPD = 11 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 1 μA (max.) at TA = 25 °C • High noise immunity: VH(typ) = 0.9 V at VCC = 5 V • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating volta

文件：477.03 Kbytes 页数：13 Pages

STMICROELECTRONICS

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Quad 2-input Schmitt NAND gate

Features • High-speed: tPD = 11 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 1 μA (max.) at TA = 25 °C • High noise immunity: VH(typ) = 0.9 V at VCC = 5 V • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating volta

文件：477.03 Kbytes 页数：13 Pages

STMICROELECTRONICS

意法半导体