丝印：HC132Y；Package：TSSOP14(automotivegrade)；Quad 2-input Schmitt NAND gate

Features • High-speed: tPD = 11 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 1 μA (max.) at TA = 25 °C • High noise immunity: VH(typ) = 0.9 V at VCC = 5 V • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating volta

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13 INPUT NAND GATE

DESCRIPTION The M54/74HC133 is a high speed CMOS 13-INPUT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 7 stages including buffer output, which gives high no

文件：237.55 Kbytes 页数：10 Pages

STMICROELECTRONICS

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13 INPUT NAND GATE

DESCRIPTION The M54/74HC133 is a high speed CMOS 13-INPUT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 7 stages including buffer output, which gives high no

文件：237.55 Kbytes 页数：10 Pages

STMICROELECTRONICS

意法半导体

13 INPUT NAND GATE

DESCRIPTION The M54/74HC133 is a high speed CMOS 13-INPUT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 7 stages including buffer output, which gives high no

文件：237.55 Kbytes 页数：10 Pages

STMICROELECTRONICS

意法半导体

13 INPUT NAND GATE

DESCRIPTION The M54/74HC133 is a high speed CMOS 13-INPUT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The internal circuit is composed of 7 stages including buffer output, which gives high no

文件：237.55 Kbytes 页数：10 Pages

STMICROELECTRONICS

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3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

文件：256.38 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

文件：256.38 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

文件：256.38 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

文件：256.38 Kbytes 页数：11 Pages

STMICROELECTRONICS

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3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

文件：242.32 Kbytes 页数：10 Pages

STMICROELECTRONICS

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