Design
■ Design separation flow achieves both physical and functional isolation
between design partitions
■ Ability to disable external JTAG port
■ Error Detection (ED) Cycle Indicator to core
■ Provides a pass or fail indicator at every ED cycle
■ Provides visibility over intentional or unintentional change of configuration
random access memory (CRAM) bits
■ Ability to perform zeroization to clear contents of the FPGA logic, CRAM,
embedded memory, and AES key
■ Internal oscillator enables system monitor and health check capabilities
Increased System Integration
■ High memory-to-logic and multiplier-to-logic ratio
■ High I/O count, low-and mid-range density devices for user I/O constrained
applications
■ Adjustable I/O slew rates to improve signal integrity
■ Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X,
LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS
■ Supports the multi-value on-chip termination (OCT) calibration feature to
eliminate variations over process, voltage, and temperature (PVT)
■ Four phase-locked loops (PLLs) per device provide robust clock management and
synthesis for device clock management, external system clock management, and
I/O interfaces
■ Five outputs per PLL
■ Cascadable to save I/Os, ease PCB routing, and reduce jitter
■ Dynamically reconfigurable to change phase shift, frequency multiplication or
division, or both, and input frequency in the system without reconfiguring the
device
■ Remote system upgrade without the aid of an external controller
■ Dedicated cyclical redundancy code checker circuitry to detect single-event upset
(SEU) issues
■ Nios?
II embedded processor for Cyclone III device family, offering low cost and
custom-fit embedded processing solutions
■ Wide collection of pre-built and verified IP cores from Altera and Altera
Megafunction Partners Program (AMPP) partners
■ Supports high-speed external memory interfaces such as DDR, DDR2,
SDR SDRAM, and QDRII SRAM
■ Auto-calibrating PHY feature eases the timing closure process and eliminates
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces
Cyclone III device family supports vertical migration that allows you to migrate your
device to other devices with the same dedicated pins, configuration pins, and power
pins for a given package-across device densities. This allows you to optimize device
density and cost as your design evolves.
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专业代理，全新到货，大量现货欢迎询问！！！
质优价廉，品质保证！
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