FTSH-103-04-L-DV-TR技术资料参数供应代理-114ic电子网

型号	下载订购	功能描述	制造商上传企业	LOGO
FTSH-103-04-L-DV-TR	文件：300 bytes Page：1 Pages	排针	Samtec 美国申泰	Samtec
PLL103-04	文件：122.59 Kbytes Page：4 Pages	1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out 文件：122.59 Kbytes 页数：4 Pages	PLL	PLL
PLL103-04SC	文件：122.59 Kbytes Page：4 Pages	1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out 文件：122.59 Kbytes 页数：4 Pages	PLL	PLL
PLL103-04SI	文件：122.59 Kbytes Page：4 Pages	1-to-4 Clock Distribution Buffer DESCRIPTIONS The PLL103-04 is a 1-to-4 Clock Distribution Buffer, reproducing the reference input frequency (FIN) at 4 different outputs. It is designed to minimize skew between outputs and provides TTL and CMOS compatible output levels. An output enable selector is available to tri-state all out 文件：122.59 Kbytes 页数：4 Pages	PLL	PLL

更多FTSH-103-04-L-DV供应商更新时间2025-11-3 14:36:00