SYMPHONY™AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES Digital Signal Processing Core • Efficient, object code compatible with the 24-bit DSP56000 core engine • Up to 40.5 Million Instructions Per Second (MIPS)—24.7 ns instruction cycle at 81 MHz; up to 324 Million Operations Per Second (MOPS) at 81 MHz • Highly parallel instruction set

文件：909.28 Kbytes 页数：82 Pages

恩XP

SYMPHONY™AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES Digital Signal Processing Core • Efficient, object code compatible with the 24-bit DSP56000 core engine • Up to 40.5 Million Instructions Per Second (MIPS)—24.7 ns instruction cycle at 81 MHz; up to 324 Million Operations Per Second (MOPS) at 81 MHz • Highly parallel instruction set

文件：909.28 Kbytes 页数：82 Pages

恩XP

SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

SYMPHONY™ AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS Motorola designed the Symphony™ family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, ATRAC, and Lucasfilm Home THX processing.

文件：617.03 Kbytes 页数：82 Pages

freescaleFreescale Semiconductor, Inc

飞思卡尔飞思卡尔半导体

SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES • Efficient, object code compatible with the 24-bit DSP56000 core family engine • Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte

文件：951.69 Kbytes 页数：83 Pages

恩XP

SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES • Efficient, object code compatible with the 24-bit DSP56000 core family engine • Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte

文件：951.69 Kbytes 页数：83 Pages

恩XP

SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES • Efficient, object code compatible with the 24-bit DSP56000 core family engine • Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte

文件：951.69 Kbytes 页数：83 Pages

恩XP

SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES • Efficient, object code compatible with the 24-bit DSP56000 core family engine • Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte

文件：951.69 Kbytes 页数：83 Pages

恩XP

SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS

FEATURES • Efficient, object code compatible with the 24-bit DSP56000 core family engine • Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at 88 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte

文件：951.69 Kbytes 页数：83 Pages

恩XP

24-BIT DVD DIGITAL SIGNAL PROCESSOR

The DSP56011 is a high-performance programmable Digital Signal Processor (DSP) developed for Digital Versatile Disc (DVD), High-Definition Television (HDTV), and Advanced Set-top audio decoding. The DSP56011 is optimized with audio-specific peripherals and customized memory configuration, and may

文件：808.4 Kbytes 页数：82 Pages

Motorola

摩托罗拉

16-bit General Purpose Digital Signal Processor

The DSP56166 is the second member of Motorola’s DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal Processors (DSP). Designed primarily for speech coding and digital communications, the DSP56166 has a built-in Σ∆ codec and phase locked loop (PLL). This MPU-style DSP also co

文件：448.33 Kbytes 页数：63 Pages

Motorola

摩托罗拉