DSP56166ROM

16-bit General Purpose Digital Signal Processor

TheDSP56166isthesecondmemberofMotorola’sDSP56100familyofHCMOS,lowpower,16-bitgeneralpurposeDigitalSignalProcessors(DSP).Designedprimarilyforspeechcodinganddigitalcommunications,theDSP56166hasabuilt-inΣ∆codecandphaselockedloop(PLL).ThisMPU-styleDSPalsoco

DSP56300

24-Bit Digital Signal Processor

Features •80/100millioninstructionspersecond(MIPS)witha80/100MHzclockat3.0–3.6V •ObjectcodecompatiblewiththeDSP56000corewithhighlyparallelinstructionset •DataArithmeticLogicUnit(DataALU)withfullypipelined24×24-bitparallelMultiplier- Accumulator(MAC),56

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DSP56300

24-Bit Digital Signal Processor

Features High-PerformanceDSP56300Core •80/100millioninstructionspersecond(MIPS)witha80/100MHzclockat3.0–3.6V •ObjectcodecompatiblewiththeDSP56000corewithhighlyparallelinstructionset •DataArithmeticLogicUnit(DataALU)withfullypipelined24´24-bitparallel M

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DSP56300

DSP56307EVM Evaluation Module

FEATURES Hardware •24-bitDSP56307DigitalSignalProcessor –High-PerformanceDSP56300core •100MillionInstructionsPerSecond(MIPS)witha100-MHzclockat2.5-Vcoreand 3.3VI/O •ObjectcodecompatiblewiththeDSP56000core •Highly-parallelinstructionset •DataArithmeticL

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DSP56300

24-Bit Digital Signal Processor

DSP56321TFeatures High-PerformanceDSP56300Core •220/240millionmultiply-accumulatespersecond(MMACS)(440/480MMACSusingtheEFCOPin filteringapplications)witha220/240MHzclockat1.6Vcoreand3.3VI/Oandajunction temperaturerangeof0–85°C •Objectcodecompatiblewitht

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DSP56300

The DSP56371 is a high density CMOS device with 5.0-V compatible inputs and outputs

DSP56300CoreDescription TheDSP56371usestheDSP56300core,ahigh-performance,singleclockcycleperinstructionenginethat providesuptotwicetheperformanceofMotorola'spopularDSP56000corefamilywhileretainingcode compatibilitywithit. TheDSP56300corefamilyoffersanewle

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DSP56300

24-Bit Audio Digital Signal Processor

Overview ThisdocumentbrieflydescribestheDSP5636724-bitdigitalsignalprocessor(DSP).TheDSP56367isamemberoftheDSP56300familyofprogrammableCMOSDSPs.TheDSP56367istargetedtoapplicationsthatrequiredigitalaudiocompression/decompression,soundfieldprocessing,acoustice

DSP56300

Implementing Viterbi Decoders Using the VSL Instruction on DSP Families

24-BitDigitalSignalProcessor TheDSP56309isamemberoftheDSP56300corefamilyofprogrammableCMOSDSPs.TheDSP56300core includesabarrelshifter,24-bitaddressing,aninstructioncache,anddirectmemoryaccess(DMA).TheDSP56309 offers100MMACSat3.0–3.6Vusinganinter

DSP56300FM

24-Bit Audio Digital Signal Processor

Overview ThisdocumentbrieflydescribestheDSP5636724-bitdigitalsignalprocessor(DSP).TheDSP56367isamemberoftheDSP56300familyofprogrammableCMOSDSPs.TheDSP56367istargetedtoapplicationsthatrequiredigitalaudiocompression/decompression,soundfieldprocessing,acoustice

DSP56300FM

24-Bit Audio Digital Signal Processor

Overview TheDSP56364supportsdigitalaudioapplicationsrequiringsoundfieldprocessing,acousticequalization,andotherdigitalaudioalgorithms. Features DigitalSignalProcessingCore •100MillionInstructionsPerSecond(MIPS)withan100MHzclockat3.3V. •ObjectCodeCompatiblew