256/512/1K/2K/4K x 9 Asynchronous FIFO

文件：622.02 Kbytes 页数：17 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

256/512/1K/2K/4K x 9 Asynchronous FIFO

Infineon

英飞凌

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port ha

文件：874.09 Kbytes 页数：30 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port ha

文件：874.09 Kbytes 页数：30 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the inpu

文件：879.91 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the inpu

文件：879.91 Kbytes 页数：29 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

文件：771.86 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

文件：771.86 Kbytes 页数：24 Pages

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

同步 SRAM

Infineon

英飞凌

同步 SRAM

Infineon

英飞凌