18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the inpu

文件：879.91 Kbytes 页数：29 Pages

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description\nThe CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K ■ 18-Mbit density (1 M × 18, 512 K × 36)\n■ 550-MHz clock for high bandwidth\n■ Two-word burst for reducing address bus frequency\n■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz\n■ Available in 2.5 clock cycle latency\n■ Two input clocks (K and K) for precise DDR timin;

Infineon

英飞凌

双倍数据速率 (DDR) 同步 SRAM

Infineon

英飞凌

Package：165-LBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165FBGA

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Package：165-LBGA；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165FBGA

CYPRESSCypress Semiconductor

赛普拉斯赛普拉斯半导体公司