18-Mbit QDR짰 II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description The CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port ha

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CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Functional Description\nThe CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has de ■ Separate independent read and write data ports\n  ❐ Supports concurrent transactions\n■ 550-MHz clock for high bandwidth\n■ Four-word burst for reducing address bus frequency\n■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz\n■ Available in;

Infineon

英飞凌

同步 SRAM

Infineon

英飞凌

同步 SRAM

Infineon

英飞凌

Package：165-LBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165FBGA

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司

Package：165-LBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 18MBIT PARALLEL 165FBGA

CypressCypress Semiconductor

赛普拉斯赛普拉斯半导体公司