SLEEK AND SLIM, WITH SOFTLY ROUNDED CORNERS AND GENTLY CURVED ROCKERS, NEXUS COMBINES SUPERIOR QUALITY WITH STUNNING GOOD LOOK SAND EASY INSTALLATION.

10AX PLATE SWITCHES 20A SWITCHES 45A SWITCHES 13 AMP SOCKET OUTLETS ROUND PIN SOCKET OUTLETS 13 AMP FUSED CONNECTION UNITS 13 AMP FUSED CONNECTION UNITS WITH FLEX OUTLET 25 AMP FLEX OUTLET PLATE SHAVER SOCKET CO-AXIAL, SATELLITE AND TRIPLEX OUTLETS TELEPHONE & DATA OUTLETS DIMMERS SURF

文件：5.53529 Mbytes 页数：6 Pages

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7/8 Power Double-Ended Cordset: Male straight to female straight, 5-pin(4PE), orange body, 230 V AC/DC, 9 A; PVC orange cable, 0.50 mm²

Product Description 7/8 Power Double-Ended Cordset: Male straight to female straight, 5-pin(4+PE), orange body, 230 V AC/DC, 9 A; PVC orange cable, 0.50 mm²

文件：551.85 Kbytes 页数：3 Pages

BELDEN

百通

Premier Supplier of Electronic Hardware

文件：5.0379 Mbytes 页数：60 Pages

ABBATRON

Nexus Moulded Wiring Accessories

文件：56.2 Kbytes 页数：1 Pages

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丝印：873；Package：16Ld2.6x1.8UTQFN；Buck PWM Controller with Internal Compensation and External Reference Tracking

文件：835.24 Kbytes 页数：17 Pages

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丝印：87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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瑞萨

丝印：87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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瑞萨

丝印：87354AIL；Package：SOIC；÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

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瑞萨

丝印：87354AIL；Package：SOIC；÷4/÷5 Differential-to-3.3V LVPECL Clock Generator

FEATURES • One differential 3.3V LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL lev

文件：359.17 Kbytes 页数：16 Pages

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丝印：8735BMI-21LF；Package：SOIC；700MHz, Differential-to-3.3V LVPECL Zero Delay Clock Generator

Features •One differential 3.3V LVPECL output pair, one differential feedback output pair •Differential CLK, nCLK input pair •CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, HCSL •Output frequency range: 31.25MHz to 700MHz •Input frequency range: 31.25

文件：635.27 Kbytes 页数：19 Pages

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