Electronic, 2 Pr #22 Str TC, PO Ins, 1Pr w/ TC Brd, PVC Jkt, CM

Product Description Electronic, 2 Pair 22AWG (7x30) Tinned Copper, PO Insulation, 1 Pair w/ Tinned Copper Braid(62) Shield, PVC Outer Jacket, CM

文件：164.01 Kbytes 页数：2 Pages

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Low Voltage, Low Skew 3.3V LVPECL Clock Generator

Features • Ten differential 3.3V LVPECL outputs • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK1 accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz

文件：406.63 Kbytes 页数：18 Pages

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丝印：87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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瑞萨

丝印：87321AIL；Package：SOIC；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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瑞萨

÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

文件：429.9 Kbytes 页数：17 Pages

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瑞萨

丝印：ICS87322BYILF；Package：LQFP；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

文件：429.9 Kbytes 页数：17 Pages

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瑞萨

丝印：ICS87322BYILF；Package：LQFP；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

文件：429.9 Kbytes 页数：17 Pages

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瑞萨

丝印：ICS8732AY-01LF；Package：LQFP；Low Voltage, Low Skew 3.3V LVPECL Clock Generator

Features • Ten differential 3.3V LVPECL outputs • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK1 accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz

文件：406.63 Kbytes 页数：18 Pages

RENESAS

瑞萨

丝印：ICS8732AY-01LF；Package：LQFP；Low Voltage, Low Skew 3.3V LVPECL Clock Generator

Features • Ten differential 3.3V LVPECL outputs • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK1 accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz

文件：406.63 Kbytes 页数：18 Pages

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瑞萨