÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

文件：521.919 Kbytes 页数：19 Pages

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Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

文件：429.9 Kbytes 页数：17 Pages

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丝印：ICS87322BYILF；Package：LQFP；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

文件：429.9 Kbytes 页数：17 Pages

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丝印：ICS87322BYILF；Package：LQFP；Low Skew, ÷1/÷2, 3.3V LVPECL/ECL Clock Generator

FEATURES • Fifteen differential LVPECL outputs • Selectable LVPECL differential clock inputs • CLK0, nCLK0 and CLK1, nCLK1 can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: 750MHz (maximum) • Output skew: 180ps (maximum) • Bank skew: 65ps (maxi

文件：429.9 Kbytes 页数：17 Pages

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丝印：ICS8732AY-01LF；Package：LQFP；Low Voltage, Low Skew 3.3V LVPECL Clock Generator

Features • Ten differential 3.3V LVPECL outputs • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK1 accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz

文件：406.63 Kbytes 页数：18 Pages

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丝印：ICS8732AY-01LF；Package：LQFP；Low Voltage, Low Skew 3.3V LVPECL Clock Generator

Features • Ten differential 3.3V LVPECL outputs • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK1 accepts the following input levels: LVCMOS or LVTTL • Maximum output frequency: 350MHz

文件：406.63 Kbytes 页数：18 Pages

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丝印：332AI01L；Package：SOIC；÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator

FEATURES • One ÷2 differential 2.5V/3.3V LVPECL / ECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Maximum input frequency: 1GHz • Translates any single ended inpu

文件：531.21 Kbytes 页数：15 Pages

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丝印：332AI01L；Package：SOIC；÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator

FEATURES • One ÷2 differential 2.5V/3.3V LVPECL / ECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Maximum input frequency: 1GHz • Translates any single ended inpu

文件：531.21 Kbytes 页数：15 Pages

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÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator

FEATURES • One ÷2 differential 2.5V/3.3V LVPECL / ECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 500MHz • Maximum input frequency: 1GHz • Translates any single ended inpu

文件：531.21 Kbytes 页数：15 Pages

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丝印：ICS7339AI11L；Package：TSSOP；Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator

FEATURES • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Tra

文件：386.47 Kbytes 页数：16 Pages

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