丝印：V00；Package：SC-74A；Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

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NEXPERIA

安世

丝印：VA；Package：SOT-353；Single 2-input NAND gate

DESCRIPTION The 74LVC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schm

文件：86.38 Kbytes 页数：15 Pages

PHI

PHI

丝印：VA；Package：SOT-353；Single 2-input NAND gate

description The 74LVC1G00 provides the single 2-input NAND function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Schmitt trigger action at all inputs makes the circuit tolerant for slower inpu

文件：87.47 Kbytes 页数：14 Pages

恩XP

丝印：VA；Package：SOT353-1；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

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丝印：VA；Package：TSSOP5；Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

文件：232 Kbytes 页数：12 Pages

NEXPERIA

安世

丝印：VA；Package：SOT1226-3；Single 2-input NAND gate

1. General description The 74LVC1G00 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower i

文件：256.38 Kbytes 页数：16 Pages

NEXPERIA

安世

丝印：V00；Package：XSON5；Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

文件：232 Kbytes 页数：12 Pages

NEXPERIA

安世

SINGLE 2 INPUT POSITIVE NAND GATE

Features  Grade 1 Ambient Temperature Operation: -40°C to +125°C  Wide Supply Voltage Range from 1.65V to 5.5V  ±24mA Output Drive at 3.3V  CMOS Low Power Consumption  IOFF Supports Partial-Power-Down Mode Operation  Inputs Accept up to 5.5V  ESD Protection Tested per AEC-Q100  Exc

文件：528.86 Kbytes 页数：9 Pages

DIODES

美台半导体

Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

文件：232 Kbytes 页数：12 Pages

NEXPERIA

安世

Single 2-input NAND gate

1. General description The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slo

文件：232 Kbytes 页数：12 Pages

NEXPERIA

安世